The invention relates, in general, to non-volatile memory devices and, more particularly, to non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and wherein the devices can pass the limit in terms of the layout, whereby a channel length can be controlled.
Flash memory is a type of non-volatile memory that retains information stored therein even if power is off, and is largely classified into a NOR type and a NAND type.
NOR flash memory requires one contact per two cells. NOR flash memory is disadvantageous in a high level of integration, but is advantageous in high speed operation since the cell current is high. NAND flash memory is disadvantageous in high speed operation since the cell current is low, but is advantageous in a high level of integration since a number of cells share one contact. Accordingly, NAND flash memory has recently been used in digital still cameras, and so on and therefore has been in the spotlight as the next-generation memory.
Generally a flash memory cell has a structure in which a tunnel oxide layer, a floating gate, a gate dielectric layer, and a control gate are sequentially laminated on a semiconductor substrate. The program and erase operations are performed by injecting electrons into or extracting them from the floating gate. The flash memory cell is also called “floating gate memory.”
The floating gate memory is severely restricted in scale down because of a voltage-divided coupling method and an Inter-Poly Oxide (IPO) structure.
In recent years, Silicon Oxide Nitride Oxide Silicon (SONOS) type non-volatile memory, which has solved the scale-down restriction of the floating gate memory, has been in the spotlight.
The SONOS type non-volatile memory employs a difference in the electrical potential between the oxide layer and the nitride layer. This corresponds to the principle that electrons trapped at the nitride layer retain their non-volatile characteristic by the potential barrier of an underlying oxide layer without being lost, although power is off. A program operation is performed by applying a voltage through which electrons can tunnel a thin oxide layer under the nitride layer. A read operation is performed by allowing a differential amplifier to determine a difference in the driving current, which is incurred by a difference in the threshold voltage of the transistor depending on program.
In the SONOS type non-volatile memory, elements can operate without voltage dividing since there is no IPO unlike the floating gate memory. The SONOS type non-volatile memory is very simple in structure. However, it is expected that the SONOS type non-volatile memory will reach the limit of integration. Accordingly, there is a need for a technique capable of increasing the level of integration per unit pitch as well as scale-down.